1. Field of the Invention
The present invention relates to an address generating circuit and particularly to a redundant address generating circuit for storing an address of a defective memory cell (hereafter referred to as redundant address) in the memory cell array of a RAM (Random Access Memory), and generating the redundant address when the power supply of the RAM is turned ON.
2. Description of the Related Art
FIGS. 1(a) and 1(b) are schematic diagrams of an address generating circuit of the conventional art.
FIG. 1(a) is a circuit diagram illustrating an address generating circuit of the conventional art. In this figure, 41 is a first switch transistor consisting of PMOS transistor, 42 is a fuse element, 43 is a latch circuit, 44 is an inverter and 45 is a power-ON reset circuit.
In the address generating circuit of the conventional art illustrated in FIG. 1(a), a first switch transistor 41 and a fuse element 42 are connected sequentially in series between the power supply source VDD and the ground VSS. A latch circuit 43 is comprised of two inverters. The input terminal of one inverter and the output terminal of the other inverter are mutually connected. The input node of the latch circuit 43 is connected to the connection node A of the first switch transistor 41 and fuse element 42, while the output node in the opposite side is connected to the inverter 44.
The power-ON reset circuit 45 outputs a reset signal RES. The reset signal RES is inputted to the gate of the first switch transistor 41. The fuse element 42 is selectively set in the cut-off condition or no cut-off condition in accordance with the address to be generated. Thereby, the binary information can be stored.
FIG. 1(b) is a waveform diagram illustrating the waveform of the reset signal RES to be inputted to the gate of the first switch.transistor 41. In this figure, the lateral axis t indicates the time, while the vertical axis V indicates voltage and t0 indicates the time when the power supply is turned ON.
As illustrated in FIG. 1(b), when the power supply is turned ON at time t0, the potential of the power supply source VDD rises with passage of time. When it reaches the predetermined power supply voltage, for example, 3.3V, it is maintained at this power supply voltage. Meanwhile, the power-ON reset circuit 45 operates in response to such rising of the level of the power supply source VDD and outputs the reset signal RES. The reset signal RES holds the ground potential until the time t1 is delayed as much as the predetermined time from the time t0 (t0 is the time when the power supply is turned ON), and has the waveform following the rising of the level of the power supply source VDD after the time t1. Namely, the reset signal RES has the waveform whereby the level rises like a step at the time t1 as illustrated in FIG. 1(b).
Next, operations of the address generating circuit of FIG. 1(a) will be explained with reference to the waveform of the reset signal RES of FIG. 1(b).
Since the reset signal RES is held at the ground potential up to time t1 from time t0 after the power supply is turned ON, the first switch transistor 41 is turned ON. Therefore, the charges are supplied to the node A from the power supply source VDD and thereby the node A is held at a certain positive potential.
At the time t1, the level of the reset signal RES rises like a step as illustrated in FIG. 1(b) and thereby the first switch transistor 41 is turned OFF. Therefore, when the fuse element 42 is in the no cut-off condition, charges accumulated in the node A transfer to the ground VSS via the fuse element 42 and the input node of the latch circuit 43 is held at the ground potential. Meanwhile, when the fuse element 42 is in the cut-off condition, certain charges are held in the node A and the potential of the input node of the latch circuit 43 is held at the certain positive potential.
Therefore, after the power supply is turned ON, the H level or L level is latched at the latch circuit 43 in accordance with the cut-off or no cut-off condition of the fuse element 42. When the fuse element 42 is set in the cut-off condition, the H level signal is outputted to the inverter 44 from the latch circuit 43. When the fuse element 42 is set in the non cut-off condition, the L level signal is outputted to the inverter 44. Accordingly, an address (binary information) stored in the address generating circuit is outputted via the inverter 44.
However, in the address generating circuit of the conventional art explained above, during the period when the power supply is turned OFF from being turned ON, a large voltage corresponding to the power supply voltage is always applied between both ends of the fuse element 42 in the fuse element 42 during the cut-off condition. Thereby, a small amount of current flows steadily through the fuse element 42.
Namely, the fuse element 42 actually has a resistance of about several M xcexa9 even when it is in the cut-off condition. Therefore, even when the fuse element 42 is in the cut-off condition, a current path is steadily formed via the input node of the latch circuit 43, fuse element 42 and ground VSS. Since the input node of latch circuit 43 is in the H level when the fuse element 42 is in the cut-off condition, a small amount of current leaks between the node (H level) of the latch circuit 43 and the ground VSS and steadily flows in the fuse element 42 of the cut-off condition.
Due to such steady current leak, the glow-back phenomenon is caused in the material (for example, Al, Cu) of the fuse element 42. While the cycle of power supply between ON and OFF is repeated for many times, the fuse element 42 of the cut-off condition is connected again after the gradual change by the glow-back phenomenon and thereby the resistance value is reduced. As a result, a problem arises when even if the fuse is set in the cut-off condition, the address corresponding to the no cut-off condition of the fuse is generated due to erroneous data latch of the cut-off information of the fuse.
Furthermore, as the related art of the present invention, there may be a fuse ROM circuit disclosed in Japanese Patent Laid-open Publication No. 8-321197.
The fuse ROM circuit has a ROM cell where a fuse element, a first switch transistor and a second switch transistor are sequentially connected in series between the power supply source VDD and the ground VSS The connection node of the first switch transistor and the second switch transistor is connected to the node of a latch circuit. The fuse ROM circuit further has a gate control circuit which outputs a control signal for controlling the ON/OFF conditions of the first switch transistor and second switch transistor.
This gate control circuit controls the ON/OFF conditions of the first switch transistor and the second switch transistor after the power supply is turned ON and after the level of the power supply source VDD is stabilized at the predetermined voltage, for example, to 3.3V. Therefore, a longer period of time is required until the cut-off information of the fuse element is latched in the latch circuit after the power supply is turned ON.
The present invention has been proposed considering the problems explained above, and therefore it is a general objective of the present invention to provide an address generating circuit which can accurately latch the cut-off information of the fuse and output the accurate address by preventing re-connection of the fuse element due to the glow-back phenomenon even if the cycle of the power supply between the state of ON and OFF is repeated.
Another and a more specific objective of the present invention is to provide an address generating circuit comprising: a first switch transistor of which one end is connected to a power supply source and the other end is connected to a first node; a second switch transistor of which one end is connected to said first node and the other end is connected to a second node; a fuse element of which one end is connected to said second node and the other end is connected to the ground; a power-ON reset circuit for outputting a first reset signal for controlling ON/OFF conditions of said first switch transistor and a second reset signal for controlling ON/OFF conditions of said second switch transistor, and a latch circuit of which the input terminal is connected to said first node, said latch circuit latching and outputting a predetermined potential corresponding to cut-off or no cut-off condition of said fuse element, wherein said first reset signal turns ON said first switch transistor during a first period immediately after the power supply is turned ON and always holds said first switch transistor in the OFF condition after said first period is completed, wherein said second reset signal turns ON said second switch transistor at least during a second period after said first period and always holds said second switch transistor in the OFF condition after said second period is completed.
Since the second switch transistor of the present invention can be turned OFF in accordance with the second reset signal, a current path which steadily forms between the ground and the input terminal of the latch circuit during the period from turning the power supply from ON to OFF can be prevented.
Therefore, a steady leak of current flowing through the fuse element in the cut-off condition can be prevented. Furthermore, the fuse element which is cut off is again connected due to the glow-back phenomenon can also be prevented. Moreover, the accurate address can be outputted by accurately latching the cut-off information of the fuse.